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Intel 8086

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</style><table class="infobox"><caption class="infobox-title">Intel 8086</caption><tbody><tr><td colspan="2" class="infobox-image"><div class="infobox-caption">A rare Intel C8086 processor in purple ceramic DIP package with side-brazed pins</div></td></tr><tr><th colspan="2" class="infobox-header">General information</th></tr><tr><th scope="row" class="infobox-label">Launched</th><td class="infobox-data">1978</td></tr><tr><th scope="row" class="infobox-label">Discontinued</th><td class="infobox-data">1998<a href="#cite_note-1">[1]</a></td></tr><tr><th scope="row" class="infobox-label">Common manufacturer</th><td class="infobox-data"><style data-mw-deduplicate="TemplateStyles:r1126788409">

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</style><div class="plainlist"><ul><li><a href="Intel" title="Intel">Intel</a>, <a href="AMD" title="AMD">AMD</a>, <a href="NEC" title="NEC">NEC</a>, <a href="Fujitsu" title="Fujitsu">Fujitsu</a>, <a href="Harris_Corporation" title="Harris Corporation">Harris</a> (<a href="Intersil" title="Intersil">Intersil</a>), <a href="Oki_Electric_Industry" title="Oki Electric Industry">OKI</a>, <a href="Siemens" title="Siemens">Siemens</a>, <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>, <a href="Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi</a>, <a href="Panasonic" title="Panasonic">Panasonic</a> (Matsushita)</li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Performance</th></tr><tr><th scope="row" class="infobox-label">Max. <a href="Central_processing_unit" title="Central processing unit">CPU</a> <a href="Clock_rate" title="Clock rate">clock rate</a></th><td class="infobox-data">5 MHz to 10 MHz</td></tr><tr><th scope="row" class="infobox-label">Data width</th><td class="infobox-data">16 bits</td></tr><tr><th scope="row" class="infobox-label">Address width</th><td class="infobox-data">20 bits</td></tr><tr><th colspan="2" class="infobox-header">Architecture and classification</th></tr><tr><th scope="row" class="infobox-label"><a href="Technology_node" class="mw-redirect" title="Technology node">Technology node</a></th><td class="infobox-data"><a href="3_%CE%BCm_process" title="3 μm process">3 μm</a></td></tr><tr><th scope="row" class="infobox-label"><a href="Instruction_set_architecture" title="Instruction set architecture">Instruction set</a></th><td class="infobox-data"><a href="X86-16" class="mw-redirect" title="X86-16">x86-16</a></td></tr><tr><th colspan="2" class="infobox-header">Physical specifications</th></tr><tr><th scope="row" class="infobox-label"><a href="Transistor_count" title="Transistor count">Transistors</a></th><td class="infobox-data"><div class="plainlist"><ul><li>29,000<a href="#cite_note-2">[2]</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label"><a href="Co-processor" class="mw-redirect" title="Co-processor">Co-processor</a></th><td class="infobox-data"><a href="Intel_8087" title="Intel 8087">Intel 8087</a>, <a href="Intel_8089" title="Intel 8089">Intel 8089</a></td></tr><tr><th scope="row" class="infobox-label">Package</th><td class="infobox-data"><div class="plainlist"><ul><li>40 pin <a href="Dual_in-line_package" title="Dual in-line package">dual in-line package</a></li></ul></div></td></tr><tr><th scope="row" class="infobox-label">Socket</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="Dual_in-line_package" title="Dual in-line package">DIP40</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">Products, models, variants</th></tr><tr><th scope="row" class="infobox-label">Variant</th><td class="infobox-data"><div class="plainlist"><ul><li><a href="Intel_8088" title="Intel 8088">8088</a></li></ul></div></td></tr><tr><th colspan="2" class="infobox-header">History</th></tr><tr><th scope="row" class="infobox-label">Predecessor</th><td class="infobox-data"><a href="Intel_8085" title="Intel 8085">Intel 8085</a></td></tr><tr><th scope="row" class="infobox-label">Successors</th><td class="infobox-data"><a href="Intel_80186" title="Intel 80186">80186</a> and <a href="Intel_80286" title="Intel 80286">80286</a> (both of which were introduced in early 1982)</td></tr><tr><th colspan="2" class="infobox-header">Support status</th></tr><tr><td colspan="2" class="infobox-full-data">Unsupported</td></tr></tbody></table>

The 8086<a href="#cite_note-3">[3]</a> (also called iAPX 86)<a href="#cite_note-i286-4">[4]</a> is a <a href="16-bit_computing" title="16-bit computing">16-bit</a> <a href="Microprocessor" title="Microprocessor">microprocessor</a> chip released by <a href="Intel" title="Intel">Intel</a> on June 8, 1978.<a href="#cite_note-Intel-5">[5]</a> Development took place from early 1976 to 1978.<a href="#cite_note-6">[6]</a> It was followed by the <a href="Intel_8088" title="Intel 8088">Intel 8088</a> in 1979,<a href="#cite_note-7">[7]</a> which was a slightly modified chip with an external 8-bit <a href="Bus_(computing)" title="Bus (computing)">data bus</a> (allowing the use of cheaper and fewer supporting <a href="Integrated_circuit" title="Integrated circuit">ICs</a>),<a href="#cite_note-8">[note 1]</a> and is notable as the processor used in the original <a href="IBM_Personal_Computer" title="IBM Personal Computer">IBM PC</a> design.

The 8086 gave rise to the <a href="X86" title="X86">x86</a> architecture, which eventually became Intel's most successful line of processors. On June 5, 2018, Intel released a limited-edition CPU celebrating the 40th anniversary of the Intel 8086, called the <a href="Coffee_Lake" title="Coffee Lake">Intel Core i7-8086K</a>.<a href="#cite_note-Intel-5">[5]</a>

<div class="mw-heading mw-heading2"><h2 id="History">History</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Background">Background</h3></div>

In 1972, Intel launched the <a href="Intel_8008" title="Intel 8008">8008</a>, Intel's first 8-bit microprocessor.<a href="#cite_note-9">[note 2]</a> It implemented an <a href="Instruction_set" class="mw-redirect" title="Instruction set">instruction set</a> designed by <a href="Datapoint" title="Datapoint">Datapoint Corporation</a> with programmable <a href="Computer_terminal" title="Computer terminal">CRT terminals</a> in mind, which also proved to be fairly general-purpose. The device needed several additional <a href="Integrated_circuit" title="Integrated circuit">ICs</a> to produce a functional computer, in part due to it being packaged in a small 18-pin "memory package", which ruled out the use of a separate address bus (Intel was primarily a <a href="DRAM" class="mw-redirect" title="DRAM">DRAM</a> manufacturer at the time).

Two years later, Intel launched the <a href="Intel_8080" title="Intel 8080">8080</a>, employing the new 40-pin <a href="Dual_in-line_package" title="Dual in-line package">DIL packages</a> originally developed for <a href="Calculator" title="Calculator">calculator</a> ICs to enable a separate address bus. It had an extended instruction set that is <a href="Source-compatible" class="mw-redirect" title="Source-compatible">source-compatible</a> (not <a href="Binary_compatible" class="mw-redirect" title="Binary compatible">binary compatible</a>) with the 8008<a href="#cite_note-10">[8]</a> and also included some <a href="16-bit_computing" title="16-bit computing">16-bit</a> instructions to make programming easier. The 8080 device was eventually replaced by the <a href="Depletion-load_NMOS_logic" title="Depletion-load NMOS logic">depletion-load</a>-based <a href="Intel_8085" title="Intel 8085">8085</a> (1977), which used a single +5 V power supply instead of the three different operating voltages of earlier chips.<a href="#cite_note-11">[note 3]</a> Other well known 8-bit microprocessors that emerged during these years are <a href="Motorola_6800" title="Motorola 6800">Motorola 6800</a> (1974), <a href="PIC_microcontroller" class="mw-redirect" title="PIC microcontroller">General Instrument PIC16X</a> (1975), <a href="MOS_Technology_6502" title="MOS Technology 6502">MOS Technology 6502</a> (1975), <a href="Zilog_Z80" title="Zilog Z80">Zilog Z80</a> (1976), and <a href="Motorola_6809" title="Motorola 6809">Motorola 6809</a> (1978).

<div class="mw-heading mw-heading3"><h3 id="The_first_x86_design">The first x86 design</h3></div>

The 8086 project started in May 1976<a href="#cite_note-12">[9]</a> and was originally intended as a temporary substitute for the ambitious and delayed <a href="IAPX_432" class="mw-redirect" title="IAPX 432">iAPX 432</a> project. It was an attempt to draw attention from the less-delayed 16-bit and <a href="32-bit_computing" title="32-bit computing">32-bit</a> processors of other manufacturers — <a href="Motorola" title="Motorola">Motorola</a>, <a href="Zilog" title="Zilog">Zilog</a>, and <a href="National_Semiconductor" title="National Semiconductor">National Semiconductor</a>.

Whereas the 8086 was a 16-bit microprocessor, it used a similar architecture as Intel's 8-bit microprocessors (8008, 8080, and 8085). This allowed <a href="Assembly_language" title="Assembly language">assembly language</a> programs written in 8-bit to <a href="Assembly_language_translator" class="mw-redirect" title="Assembly language translator">seamlessly migrate</a>.<a href="#cite_note-Scanlon_1988-13">[10]</a> New instructions and features — such as signed integers, base+offset addressing, and self-repeating operations — were added. Instructions were added to assist source code compilation of <a href="Nested_function" title="Nested function">nested functions</a> in the <a href="ALGOL" title="ALGOL">ALGOL</a>-family of languages, including <a href="Pascal_(programming_language)" title="Pascal (programming language)">Pascal</a> and <a href="PL/M" title="PL/M">PL/M</a>. According to principal architect <a href="Stephen_P._Morse" title="Stephen P. Morse">Stephen P. Morse</a>, this was a result of a more software-centric approach. Other enhancements included <a href="Microcode" title="Microcode">microcode</a> instructions for the multiply and divide assembly language instructions. Designers also anticipated <a href="Coprocessors" class="mw-redirect" title="Coprocessors">coprocessors</a>, such as <a href="Intel_8087" title="Intel 8087">8087</a> and <a href="Intel_8089" title="Intel 8089">8089</a>, so the bus structure was designed to be flexible.

The first revision of the instruction set and high level architecture was ready after about three months,<a href="#cite_note-14">[note 4]</a> and as almost no CAD tools were used, four engineers and 12 layout people were simultaneously working on the chip.<a href="#cite_note-15">[note 5]</a> The 8086 took a little more than two years from idea to working product, which was considered fast for a complex design in the 1970s.

The 8086 was sequenced<a href="#cite_note-16">[note 6]</a> using a mixture of <a href="Random_logic" title="Random logic">random logic</a><a href="#cite_note-17">[11]</a> and <a href="Microcode" title="Microcode">microcode</a> and was implemented using depletion-load nMOS circuitry with approximately 20,000 active <a href="Transistor" title="Transistor">transistors</a> (29,000 counting all <a href="Read-only_memory" title="Read-only memory">ROM</a> and <a href="Programmable_logic_array" title="Programmable logic array">PLA</a> sites). It was soon moved to a new refined nMOS manufacturing process called <a href="HMOS" class="mw-redirect" title="HMOS">HMOS</a> (for High performance MOS) that Intel originally developed for manufacturing of fast <a href="Static_RAM" class="mw-redirect" title="Static RAM">static RAM</a> products.<a href="#cite_note-18">[note 7]</a> This was followed by HMOS-II, HMOS-III versions, and, eventually, a fully static <a href="CMOS" title="CMOS">CMOS</a> version for battery powered devices, manufactured using Intel's <a href="CHMOS" title="CHMOS">CHMOS</a> processes.<a href="#cite_note-19">[note 8]</a> The original chip measured 33 mm² and minimum feature size was 3.2 μm. The MUL and DIV instructions were very slow due to being microcoded so x86 programmers usually just used the bit shift instructions for multiplying and dividing instead.

The 8086 was die-shrunk to 2 μm in 1981; this version also corrected a stack register bug in the original 3.5 μm chips. Later 1.5 μm and CMOS variants were outsourced to other manufacturers and not developed in-house.

The architecture was defined by <a href="Stephen_P._Morse" title="Stephen P. Morse">Stephen P. Morse</a> with some help from Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic designer Jim McKevitt and John Bayliss were the lead engineers of the hardware-level development team<a href="#cite_note-20">[note 9]</a> and Bill Pohlman the manager for the project. The legacy of the 8086 is enduring in the basic instruction set of today's personal computers and servers; the 8086 also lent its last two digits to later extended versions of the design, such as the <a href="Intel_286" class="mw-redirect" title="Intel 286">Intel 286</a> and the <a href="Intel_386" class="mw-redirect" title="Intel 386">Intel 386</a>, all of which eventually became known as the <a href="X86" title="X86">x86</a> family. In addition, the <a href="PCI_Configuration_Space" class="mw-redirect" title="PCI Configuration Space">PCI Vendor ID</a> for system devices produced by Intel is 8086.<a href="#cite_note-21">[12]</a>

<div class="mw-heading mw-heading2"><h2 id="Details">Details</h2></div>

<div class="mw-heading mw-heading3"><h3 id="Buses_and_operation">Buses and operation</h3></div>

All internal registers, as well as internal and external data buses, are 16 bits wide, which firmly established the "16-bit microprocessor" identity of the 8086. A 20-bit external address bus provides a 1 <a href="Mebibyte" class="mw-redirect" title="Mebibyte">MiB</a> physical address space (220 = 1,048,576 x 1 <a href="Byte" title="Byte">byte</a>). This address space is addressed by means of internal memory "segmentation". The data bus is <a href="Multiplexed" class="mw-redirect" title="Multiplexed">multiplexed</a> with the address bus in order to fit all of the control lines into a standard 40-pin <a href="Dual_in-line_package" title="Dual in-line package">dual in-line package</a>. It provides a 16-bit I/O address bus, supporting 64 <a href="Kilobyte" title="Kilobyte">KB</a> of separate I/O space. The maximum linear address space is limited to 64 KB, simply because internal address/index registers are only 16 bits wide. Programming over 64 KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the <a href="80386" class="mw-redirect" title="80386">80386</a> architecture introduced wider (32-bit) registers (the memory management hardware in the <a href="80286" class="mw-redirect" title="80286">80286</a> did not help in this regard, as its registers are still only 16 bits wide).

<div class="mw-heading mw-heading3"><h3 id="Hardware_modes_of_8086">Hardware modes of 8086</h3></div>

Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in min or max mode. The former mode is intended for small single-processor systems, while the latter is for medium or large systems using more than one processor (a kind of multiprocessor mode). Maximum mode is required when using an 8087 or 8089 coprocessor. The voltage on pin 33 (MN/MX) determines the mode. Changing the state of pin 33 changes the function of certain other pins, most of which have to do with how the CPU handles the (local) bus.<a href="#cite_note-22">[note 10]</a> The mode is usually hardwired into the circuit and therefore cannot be changed by software. The workings of these modes are described in terms of timing diagrams in Intel datasheets and manuals. In minimum mode, all control signals are generated by the 8086 itself.

<div class="mw-heading mw-heading3"><h3 id="Registers_and_instruction">Registers and instruction</h3></div>

<caption>Intel 8086 registers

</caption>

<td>

<td style="width:10px; text-align:center;">19

</td>

<td style="width:10px; text-align:center;">18

</td>

<td style="width:10px; text-align:center;">17

</td>

<td style="width:10px; text-align:center;">16

</td>

<td style="width:10px; text-align:center;">15

</td>

<td style="width:10px; text-align:center;">14

</td>

<td style="width:10px; text-align:center;">13

</td>

<td style="width:10px; text-align:center;">12

</td>

<td style="width:10px; text-align:center;">11

</td>

<td style="width:10px; text-align:center;">10

</td>

<td style="width:10px; text-align:center;">09

</td>

<td style="width:10px; text-align:center;">08

</td>

<td style="width:10px; text-align:center;">07

</td>

<td style="width:10px; text-align:center;">06

</td>

<td style="width:10px; text-align:center;">05

</td>

<td style="width:10px; text-align:center;">04

</td>

<td style="width:10px; text-align:center;">03

</td>

<td style="width:10px; text-align:center;">02

</td>

<td style="width:10px; text-align:center;">01

</td>

<td style="width:10px; text-align:center;">00

</td>

<td style="width:auto; background:white; color:black">(bit position)

</td></tr>

<tr>

<td colspan="21">Main registers

</td></tr>

</td>

<td style="text-align:center;" colspan="8">AH

</td>

<td style="text-align:center;" colspan="8">AL

</td>

<td style="background:white; color:black;"><a href="Accumulator_(computing)" title="Accumulator (computing)">AX</a> (primary accumulator)

</td></tr>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

<td style="text-align:center;" colspan="8">BH

</td>

<td style="text-align:center;" colspan="8">BL

</td>

<td style="background:white; color:black;">BX (base, accumulator)

</td></tr>

</td>

<td style="text-align:center;" colspan="8">CH

</td>

<td style="text-align:center;" colspan="8">CL

</td>

<td style="background:white; color:black;">CX (counter, accumulator)

</td></tr>

</td>

<td style="text-align:center;" colspan="8">DH

</td>

<td style="text-align:center;" colspan="8">DL

</td>

<td style="background:white; color:black;">DX (accumulator, extended acc)

</td></tr>

<tr>

<td colspan="21">Index registers

</td></tr>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

</td>

<td style="background:white; color:black;">Source Index

</td></tr>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

<td style="text-align:center;" colspan="16">DI

</td>

<td style="background:white; color:black;">Destination Index

</td></tr>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

<td style="text-align:center;" colspan="16">BP

</td>

<td style="background:white; color:black;">Base Pointer

</td></tr>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

</td>

<td style="background:white; color:black;">Stack Pointer

</td></tr>

<tr>

<td colspan="21">Program counter

</td></tr>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

</td>

<td style="background:white; color:black;">Instruction Pointer

</td></tr>

<tr>

<td colspan="21">Segment registers

</td></tr>

<td style="text-align:center;" colspan="16">CS

</td>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

<td style="background:white; color:black;">Code Segment

</td></tr>

<td style="text-align:center;" colspan="16">DS

</td>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

<td style="background:white; color:black;">Data Segment

</td></tr>

<td style="text-align:center;" colspan="16">ES

</td>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

<td style="background:white; color:black;">Extra Segment

</td></tr>

<td style="text-align:center;" colspan="16">SS

</td>

<td style="text-align:center;background:#DDD" colspan="4">0 0 0 0

</td>

<td style="background:white; color:black;">Stack Segment

</td></tr>

<tr>

<td colspan="21">Status register

</td></tr>

</td>

<td style="text-align:center;">-

</td>

<td style="text-align:center;">-

</td>

<td style="text-align:center;">-

</td>

<td style="text-align:center;">-

</td>

</td>

</td>

</td>

</td>

</td>

</td>

<td style="text-align:center;">-

</td>

</td>

<td style="text-align:center;">-

</td>

</td>

<td style="text-align:center;">-

</td>

</td>

<td style="background:white; color:black">Flags

</td></tr></tbody></table>

The 8086 has eight more-or-less general 16-bit <a href="Processor_register" title="Processor register">registers</a> (including the <a href="Stack-based_memory_allocation" title="Stack-based memory allocation">stack pointer</a> but excluding the instruction pointer, flag register and segment registers). Four of them, AX, BX, CX, DX, can also be accessed as 8-bit register pairs (see figure) while the other four, SI, DI, BP, SP, are 16-bit only.

Due to a compact encoding inspired by 8-bit processors, most instructions are one-address or two-address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the destination, while the other operand, the source, can be either register or immediate. A single memory location can also often be used as both source and destination which, among other factors, further contributes to a <a href="Code_density" class="mw-redirect" title="Code density">code density</a> comparable to (and often better than) most eight-bit machines at the time.

The degree of generality of most registers is much greater than in the 8080 or 8085. However, 8086 registers were more specialized than in most contemporary <a href="Minicomputer" title="Minicomputer">minicomputers</a> and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this makes register allocation for compilers more complicated compared to more orthogonal 16-bit and 32-bit processors of the time such as the <a href="PDP-11" title="PDP-11">PDP-11</a>, <a href="VAX" title="VAX">VAX</a>, <a href="68000" class="mw-redirect" title="68000">68000</a>, <a href="32016" class="mw-redirect" title="32016">32016</a>, etc. On the other hand, being more regular than the rather minimalistic but ubiquitous 8-bit microprocessors such as the <a href="MOS_Technology_6502" title="MOS Technology 6502">6502</a>, <a href="Motorola_6800" title="Motorola 6800">6800</a>, <a href="6809" class="mw-redirect" title="6809">6809</a>, <a href="Intel_8085" title="Intel 8085">8085</a>, <a href="MCS-48" class="mw-redirect" title="MCS-48">MCS-48</a>, <a href="Intel_8051" class="mw-redirect" title="Intel 8051">8051</a>, and other contemporary accumulator-based machines, it is significantly easier to construct an efficient <a href="Code_generation_(compiler)" title="Code generation (compiler)">code generator</a> for the 8086 architecture.

Another factor for this is that the 8086 also introduced some new instructions (not present in the 8080 and 8085) to better support stack-based high-level programming languages such as Pascal and <a href="PL/M" title="PL/M">PL/M</a>; some of the more useful instructions are <code>push mem-op</code>, and ret size, supporting the "Pascal <a href="Calling_convention" title="Calling convention">calling convention</a>" directly. (Several others, such as <code>push immed</code> and <code>enter</code>, were added in the subsequent 80186, 80286, and 80386 processors.)

A 64 KB (one segment) <a href="Stack_(data_structure)" class="mw-redirect" title="Stack (data structure)">stack</a> growing towards lower addresses is supported in <a href="Computer_hardware" title="Computer hardware">hardware</a>; 16-bit words are pushed onto the stack, and the top of the stack is pointed to by SS:SP. There are 256 <a href="Interrupt" title="Interrupt">interrupts</a>, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the <a href="Return_address_(computing)" class="mw-redirect" title="Return address (computing)">return addresses</a>.

The 8086 has 64 K of 8-bit (or alternatively 32 K of 16-bit word) <a href="I/O_port" class="mw-redirect" title="I/O port">I/O port</a> space.

<div class="mw-heading mw-heading3"><h3 id="Flags">Flags</h3></div>

The 8086 has a 16-bit <a href="Status_register" title="Status register">flags register</a>. Nine of these condition code flags are active, and indicate the current state of the processor: <a href="Carry_flag" title="Carry flag">Carry flag</a> (CF), <a href="Parity_flag" title="Parity flag">Parity flag</a> (PF), <a href="Auxiliary_flag" class="mw-redirect" title="Auxiliary flag">Auxiliary carry flag</a> (AF), <a href="Zero_flag" title="Zero flag">Zero flag</a> (ZF), <a href="Sign_flag" class="mw-redirect" title="Sign flag">Sign flag</a> (SF), <a href="Trap_flag" title="Trap flag">Trap flag</a> (TF), <a href="IF_(x86_flag)" class="mw-redirect" title="IF (x86 flag)">Interrupt flag</a> (IF), <a href="Direction_flag" title="Direction flag">Direction flag</a> (DF), and <a href="Overflow_flag" title="Overflow flag">Overflow flag</a> (OF).

Also referred to as the status word, the layout of the flags register is as follows:<a href="#cite_note-23">[13]</a>

<th>Bit

</th>

<td>15-12

</td>

<td>11

</td>

<td>10

</td>

<td>9

</td>

<td>8

</td>

<td>7

</td>

<td>6

</td>

<td>5

</td>

<td>4

</td>

<td>3

</td>

<td>2

</td>

<td>1

</td>

<td>0

</td></tr>

<tr>

<th>Flag

</th>

<td>

</td>

<td>OF

</td>

<td>DF

</td>

<td>IF

</td>

<td>TF

</td>

<td>SF

</td>

<td>ZF

</td>

<td>

</td>

<td>AF

</td>

<td>

</td>

<td>PF

</td>

<td>

</td>

<td>CF

</td></tr></tbody></table>

<div class="mw-heading mw-heading3"><h3 id="Segmentation">Segmentation</h3></div>

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</style><div role="note" class="hatnote navigation-not-searchable">See also: <a href="X86_memory_segmentation" title="X86 memory segmentation">x86 memory segmentation</a></div>

There are also four 16-bit <a href="X86_memory_segmentation" title="X86 memory segmentation">segment</a> registers (see figure) that allow the 8086 <a href="Central_processing_unit" title="Central processing unit">CPU</a> to access one <a href="Megabyte" title="Megabyte">megabyte</a> of memory in an unusual way. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeds their register size, the 8086 shifts the 16-bit segment four bits left before adding it to the 16-bit offset (16×segment + offset), therefore producing a 20-bit external (or effective or physical) address from the 32-bit segment:offset pair. As a result, any external address could be referred to by up to 212 = 4096 different segment:offset pairs.<a href="#cite_note-24">[14]</a>

</td>

<td>Segment,

</td>

<td>16 bits, shifted 4 bits left (or multiplied by 0x10)

</td></tr>

<tr>

</td>

<td>Offset,

</td>

<td>16 bits

</td></tr>

</td>

<td>

</td></tr>

<tr>

</td>

<td>Address,

</td>

<td>20 bits

</td></tr></tbody></table>

Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 64 KB) can be loaded starting at a fixed offset (such as 0000) in its own segment, avoiding the need for <a href="Relocation_(computing)" title="Relocation (computing)">relocation</a>, with at most 15 bytes of alignment waste.

Compilers for the 8086 family commonly support two types of <a href="Pointer_(computer_programming)" title="Pointer (computer programming)">pointer</a>, near and far. Near pointers are 16-bit offsets implicitly associated with the program's code or data segment and so can be used only within parts of a program small enough to fit in one segment. Far pointers are 32-bit segment:offset pairs resolving to 20-bit external addresses. Some compilers also support huge pointers, which are like far pointers except that <a href="Pointer_arithmetic" class="mw-redirect" title="Pointer arithmetic">pointer arithmetic</a> on a huge pointer treats it as a linear 20-bit pointer, while pointer arithmetic on a far pointer <a href="Integer_overflow" title="Integer overflow">wraps around</a> within its 16-bit offset without touching the segment part of the address.

To avoid the need to specify near and far on numerous pointers, data structures, and functions, compilers also support "memory models" which specify default pointer sizes. The tiny (max 64K), small (max 128K), compact (data > 64K), medium (code > 64K), large (code,data > 64K), and huge (individual arrays > 64K) models cover practical combinations of near, far, and huge pointers for code and data. The tiny model means that code and data are shared in a single segment, just as in most 8-bit based processors, and can be used to build <a href="COM_file" title="COM file">.com</a> files for instance. Precompiled libraries often come in several versions compiled for different memory models.

According to Morse et al.,.<a href="#cite_note-25">[15]</a> the designers actually contemplated using an 8-bit shift (instead of 4-bit), in order to create a 16 MB physical address space. However, as this would have forced segments to begin on 256-byte boundaries, and 1 MB was considered very large for a microprocessor around 1976, the idea was dismissed. Also, there were not enough pins available on a low cost 40-pin package for the additional four address bus pins.

In principle, the address space of the x86 series could have been extended in later processors by increasing the shift value, as long as applications obtained their segments from the operating system and did not make assumptions about the equivalence of different segment:offset pairs.<a href="#cite_note-26">[note 11]</a> In practice the use of "huge" pointers and similar mechanisms was widespread and the flat 32-bit addressing made possible with the 32-bit offset registers in the 80386 eventually extended the limited addressing range in a more general way.

The instruction stream is fetched from memory as words and is addressed internally by the processor to the byte level as necessary. An instruction stream queuing mechanism allows up to 6 bytes of the instruction stream to be queued while waiting for decoding and execution. The queue acts as a First-In-First-Out (FIFO) buffer, from which the Execution Unit (EU) extracts instruction bytes as required. Whenever there is space for at least two bytes in the queue, the BIU will attempt a word fetch memory cycle. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.<a href="#cite_note-8086Datasheet-27">[16]</a>

<div class="mw-heading mw-heading4"><h4 id="Porting_older_software">Porting older software</h4></div>

Small programs could ignore the segmentation and just use plain 16-bit addressing. This allows <a href="8-bit_computing" title="8-bit computing">8-bit</a> software to be quite easily ported to the 8086. The authors of most <a href="DOS" title="DOS">DOS</a> implementations took advantage of this by providing an <a href="Application_Programming_Interface" class="mw-redirect" title="Application Programming Interface">Application Programming Interface</a> very similar to <a href="CP/M" title="CP/M">CP/M</a> as well as including the simple .com executable file format, identical to CP/M. This was important when the 8086 and MS-DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform.

<div class="mw-heading mw-heading3"><h3 id="Interrupts">Interrupts</h3></div>

<a href="Interrupt" title="Interrupt">Interrupts</a> on the 8086 are can be either software or hardware-initiated. Interrupts are long calls that also save the processor status. Interrupt routines typically end with a <code>IRET</code> instruction. All interrupts have a 8-bit interrupt number associated with them. This number is used to look up a segment:offset in a 256 element <a href="Interrupt_vector_table" title="Interrupt vector table">interrupt vector table</a> stored at addresses 0-3FFH. When any type of interrupt is encountered, the processor status is pushed, CS and IP are pushed, and the interrupt number is multiplied by four to index a new execution address which is loaded from the vector table.

There are three types of software interrupt instructions: <code><a href="INT_(x86_instruction)" title="INT (x86 instruction)">INT</a> n</code>, <code>INTO</code>, and a single-byte <code>INT 3</code> used for debugging.

There are two kinds of hardware interrupts: maskable and non-maskable.

Non-maskable interrupts are higher priority than maskable interrupts. They cannot be disabled by interrupt enable. A low to high transition on the NMI pin essentially causes an <code>INT 2</code> to execute.

Maskable interrupts are enabled and disabled by the <code>STI</code> and <code>CLI</code> instructions respectively. When the INTR is asserted by a hardware device, the 8086 asserts INTA twice, reading an 8-bit interrupt number from the bus. This number is multiplied by four to point to the associated interrupt service routine in the vector table. Maskable interrupts are disabled when INTA is asserted, but are re-enabled upon executing the <code>IRET</code> instruction at the end of the interrupt service routine.<a href="#cite_note-8086Datasheet-27">[16]</a>

<div class="mw-heading mw-heading2"><h2 id="Example_code">Example code</h2></div>

The following 8086 <a href="Assembly_language" title="Assembly language">assembly</a> source code is for a subroutine named <code>_strtolower</code> that copies a null-terminated <a href="ASCIIZ" class="mw-redirect" title="ASCIIZ">ASCIIZ</a> character string from one location to another, converting all alphabetic characters to lower case. The string is copied one byte (8-bit character) at a time.

<td>

<pre>

0000

0000 55

0001 89 E5

0003 56

0004 57

0005 8B 75 06

0008 8B 7D 04

000B FC

000C AC

000D 3C 41

000F 7C 06

0011 3C 5A

0013 7F 02

0015 04 20

0017 AA

0018 08 C0

001A 75 F0

001C 5F

001D 5E

001E 5D

001F C3

001F

</pre>

</td>

<td>

<div class="mw-highlight mw-highlight-lang-nasm mw-content-ltr" dir="ltr"><pre>; _strtolower:

; Copy a null-terminated ASCII string, converting

; all alphabetic characters to lower case.

; ES=DS

; Entry stack parameters

; [SP+4] = src, Address of source string

; [SP+2] = dst, Address of target string

; [SP+0] = Return address

;

_strtolower proc

push bp ;Set up the call frame

mov bp,sp

push si

push di

mov si,[bp+6] ;Set si = src (+2 due to push bp)

mov di,[bp+4] ;Set di = dst

cld ;string direction ascending

loop: lodsb ;Load al from [si], inc si

cmp al,'A' ;If al < 'A',

jl copy ; skip conversion

cmp al,'Z' ;If al > 'Z',

jg copy ; skip conversion

add al,'a'-'A' ;Convert al to lowercase

copy: stosb ;Store al to es:[di], inc di

or al,al ;If al <> 0,

jne loop ; repeat the loop

done: pop di ;restore di and si

pop si

pop bp ;Restore the prev call frame

ret ;Return to caller

end proc

</pre></div>

</td></tr></tbody></table>

The example code uses the BP (base pointer) register to establish a <a href="Call_frame" class="mw-redirect" title="Call frame">call frame</a>, an area on the stack that contains all of the parameters and local variables for the execution of the subroutine. This kind of <a href="Calling_convention" title="Calling convention">calling convention</a> supports <a href="Reentrancy_(computing)" title="Reentrancy (computing)">reentrant</a> and <a href="Recursion_(computer_science)" title="Recursion (computer science)">recursive</a> code and has been used by Algol-like languages since the late 1950s. A flat memory model is assumed, specifically, that the DS and ES segments address the same region of memory.

<div class="mw-heading mw-heading3"><h3 id="Performance">Performance</h3></div>

Although partly shadowed by other design choices in this particular chip, the <a href="Multiplexed" class="mw-redirect" title="Multiplexed">multiplexed</a> address and <a href="Bus_(computing)" title="Bus (computing)">data buses</a> limit performance slightly; transfers of 16-bit or 8-bit quantities are done in a four-clock memory access cycle, which is faster on 16-bit, although slower on 8-bit quantities, compared to many contemporary 8-bit based CPUs. As instructions vary from one to six bytes, fetch and execution are made <a href="Concurrency_(computer_science)" title="Concurrency (computer science)">concurrent</a> and decoupled into separate units (as it remains in today's x86 processors): The bus interface unit feeds the instruction stream to the execution unit through a 6-byte prefetch queue (a form of loosely coupled <a href="Pipeline_(computing)" title="Pipeline (computing)">pipelining</a>), speeding up operations on <a href="Processor_register" title="Processor register">registers</a> and <a href="Operand" title="Operand">immediates</a>, while memory operations became slower (four years later, this performance problem was fixed with the <a href="80186" class="mw-redirect" title="80186">80186</a> and <a href="80286" class="mw-redirect" title="80286">80286</a>). However, the full (instead of partial) 16-bit architecture with a full width <a href="Arithmetic_logic_unit" title="Arithmetic logic unit">ALU</a> meant that 16-bit arithmetic instructions could now be performed with a single ALU cycle (instead of two, via internal carry, as in the 8080 and 8085), speeding up such instructions considerably. Combined with <a href="Orthogonalization" title="Orthogonalization">orthogonalizations</a> of operations versus <a href="Operand" title="Operand">operand</a> types and <a href="Addressing_mode" title="Addressing mode">addressing modes</a>, as well as other enhancements, this made the performance gain over the 8080 or 8085 fairly significant, despite cases where the older chips may be faster (see below).

<caption>Execution times for typical instructions (in clock cycles)<a href="#cite_note-28">[17]</a>

</caption>

<th align="left">instruction

</th>

<th align="left">register-register

</th>

<th align="left">register immediate

</th>

<th align="left">register-memory

</th>

<th align="left">memory-register

</th>

<th align="left">memory-immediate

</th></tr>

<td>10+EA

</td></tr>

<td>17+EA

</td></tr>

<td colspan="5">register ≥ 11 ; label ≥ 15 ; condition,label ≥ 16

</td></tr>

<td>integer multiply</td>

<td colspan="5">70~160 (depending on operand data as well as size) including any EA

</td></tr>

<td>integer divide</td>

<td colspan="5">80~190 (depending on operand data as well as size) including any EA

</td></tr></tbody></table>

<ul><li>EA = time to compute effective address, ranging from 5 to 12 cycles.</li>

<li>Timings are best case, depending on prefetch status, instruction alignment, and other factors.</li></ul>

As can be seen from these tables, operations on registers and immediates were fast (between 2 and 4 cycles), while memory-operand instructions and jumps were quite slow; jumps took more cycles than on the simple <a href="Intel_8080" title="Intel 8080">8080</a> and <a href="Intel_8085" title="Intel 8085">8085</a>, and the 8088 (used in the IBM PC) was additionally hampered by its narrower bus. The reasons why most memory related instructions were slow were threefold:

<ul><li>Loosely coupled fetch and execution units are efficient for instruction prefetch, but not for jumps and random data access (without special measures).</li>

<li>No dedicated address calculation adder was afforded; the microcode routines had to use the main ALU for this (although there was a dedicated segment + offset adder).</li>

<li>The address and data buses were <a href="Multiplexing" title="Multiplexing">multiplexed</a>, forcing a slightly longer (33~50%) bus cycle than in typical contemporary 8-bit processors.</li></ul>

However, memory access performance was drastically enhanced with Intel's next generation of 8086 family CPUs. The <a href="Intel_80186" title="Intel 80186">80186</a> and <a href="Intel_80286" title="Intel 80286">80286</a> both had dedicated address calculation hardware, saving many cycles, and the 80286 also had separate (non-multiplexed) address and data buses.

<div class="mw-heading mw-heading3"><h3 id="Floating_point">Floating point</h3></div>

The 8086/8088 could be connected to a mathematical coprocessor to add hardware/microcode-based <a href="Floating-point" class="mw-redirect" title="Floating-point">floating-point</a> performance. The <a href="Intel_8087" title="Intel 8087">Intel 8087</a> was the standard math coprocessor for the 8086 and 8088, operating on 80-bit numbers. Manufacturers like <a href="Cyrix" title="Cyrix">Cyrix</a> (8087-compatible) and <a href="Weitek" title="Weitek">Weitek</a> (not 8087-compatible) eventually came up with high-performance floating-point coprocessors that competed with the 8087.

<div class="mw-heading mw-heading2"><h2 id="Chip_versions">Chip versions</h2></div>

The clock frequency was originally limited to 5 MHz,<a href="#cite_note-29">[note 12]</a> but the last versions in <a href="HMOS" class="mw-redirect" title="HMOS">HMOS</a> were specified for 10 MHz. HMOS-III and <a href="CMOS" title="CMOS">CMOS</a> versions were manufactured for a long time (at least a while into the 1990s) for <a href="Embedded_system" title="Embedded system">embedded systems</a>, although its successor, the <a href="Intel_80186" title="Intel 80186">80186</a>/<a href="Intel_80188" class="mw-redirect" title="Intel 80188">80188</a> (which includes some on-chip peripherals), has been more popular for embedded use.

The 80C86, the CMOS version of the 8086, was used in many portable computers and embedded systems, including the <a href="GridPad" title="GridPad">GridPad</a>, <a href="Toshiba_T1200" title="Toshiba T1200">Toshiba T1200</a>, <a href="HP_110" title="HP 110">HP 110</a>, and finally the 1998–1999 <a href="Lunar_Prospector" title="Lunar Prospector">Lunar Prospector</a>.

For the packaging, the Intel 8086 was available both in ceramic and plastic DIP packages.

<div class="gallerytext">A ceramic D8086 variant</div>

</li>

<div class="gallerytext">A plastic P8086 variant</div>

</li>

</ul>

<div class="mw-heading mw-heading3"><h3 id="List_of_Intel_8086">List of Intel 8086</h3></div>

<th>Model number

</th>

<th>Frequency

</th>

<th>Technology

</th>

<th>Temperature range

</th>

<th>Package

</th>

<th>Date of release

</th>

<th>Price (USD)<a href="#cite_note-30">[list2 1]</a>

</th></tr>

<tr>

<td>8086

</td>

</td>

<td>HMOS

</td>

</td>

<td>

</td>

</td>

</td></tr>

<tr>

<td>8086-1

</td>

<td>10 MHz

</td>

<td>HMOS II

</td>

<td>Commercial

</td>

<td>

</td>

<td>

</td>

<td>

</td></tr>

<tr>

<td>8086-2

</td>

</td>

<td>HMOS II

</td>

<td>Commercial

</td>

<td>

</td>

<td>January/February 1980<a href="#cite_note-IntelPrevJan80p22-35">[22]</a>

</td>

</td></tr>

<tr>

<td>8086-4

</td>

</td>

<td>HMOS

</td>

<td>Commercial

</td>

<td>

</td>

<td>

</td>

</td></tr>

<tr>

<td>I8086

</td>

<td>5 MHz

</td>

<td>HMOS

</td>

<td>Industrial −40 °C to +85 °C<a href="#cite_note-Intel_Preview_Special_Issue_1980,_page_29-32">[19]</a>

</td>

<td>

</td>

</td>

</td></tr>

<tr>

<td>M8086

</td>

<td>5 MHz

</td>

<td>HMOS

</td>

<td>Military grade −55 °C to +125 °C<a href="#cite_note-39">[25]</a>

</td>

<td>

</td>

<td>

</td>

<td>

</td></tr>

<tr>

</td>

<td>

</td>

<td>CMOS

</td>

<td>

</td>

</td>

<td>

</td>

<td>

</td></tr></tbody></table>

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</style><div class="reflist">

<li id="cite_note-30"><a href="#cite_ref-30">^</a> In quantity of 100.

</li>

<li id="cite_note-37"><a href="#cite_ref-37">^</a> Price reduced by 21% from USD $99.00, no information in quantity value listed.

</li>

<li id="cite_note-41"><a href="#cite_ref-41">^</a> Sampling Q4 1985

</li>

</ol></div></div>

<div class="mw-heading mw-heading3"><h3 id="Derivatives_and_clones">Derivatives and clones</h3></div>

Compatible—and, in many cases, enhanced—versions were manufactured by <a href="Fujitsu" title="Fujitsu">Fujitsu</a>,<a href="#cite_note-43">[28]</a> <a href="Harris_Corporation" title="Harris Corporation">Harris</a>/<a href="Intersil" title="Intersil">Intersil</a>, <a href="Oki_Electric_Industry" title="Oki Electric Industry">OKI</a>, <a href="Siemens" title="Siemens">Siemens</a>, <a href="Texas_Instruments" title="Texas Instruments">Texas Instruments</a>, <a href="NEC" title="NEC">NEC</a>, <a href="Mitsubishi_Electric" title="Mitsubishi Electric">Mitsubishi</a>, and <a href="AMD" title="AMD">AMD</a>. For example, the <a href="NEC_V20" title="NEC V20">NEC V20</a> and <a href="NEC_V30" class="mw-redirect" title="NEC V30">NEC V30</a> pair were hardware-compatible with the 8088 and 8086 even though NEC made original Intel clones μPD8088D and μPD8086D respectively, but incorporated the instruction set of the 80186 along with some (but not all) of the 80186 speed enhancements, providing a drop-in capability to upgrade both instruction set and processing speed without manufacturers having to modify their designs. Such relatively simple and low-power 8086-compatible processors in CMOS are still used in embedded systems.

The electronics industry of the <a href="Soviet_Union" title="Soviet Union">Soviet Union</a> was able to replicate the 8086 through both <a href="Industrial_espionage" title="Industrial espionage">industrial espionage</a> and reverse engineering. The resulting chip, <a href="K1810VM86" title="K1810VM86">K1810VM86</a>, was binary and pin-compatible with the 8086.

i8086 and i8088 were respectively the cores of the Soviet-made PC-compatible EC1831 and EC1832 desktops. (EC1831 is the EC identification of IZOT 1036C and EC1832 is the EC identification of IZOT 1037C, developed and manufactured in Bulgaria. EC stands for Единая Система.) However, the EC1831 computer (IZOT 1036C) had significant hardware differences from the IBM PC prototype. The EC1831 was the first PC-compatible computer with dynamic bus sizing (US Pat. No 4,831,514). Later some of the EC1831 principles were adopted in PS/2 (US Pat. No 5,548,786) and some other machines (UK Patent Application, Publication No. GB-A-2211325, Published June 28, 1989).

<div class="gallerytext">Soviet clone <a href="K1810VM86" title="K1810VM86">K1810VM86</a></div>

</li>

</li>

<div class="gallerytext">NEC μPD8086D-2 (8 MHz) from the year 1984, week 19 JAPAN (clone of Intel D8086-2)</div>

</li>

</li>

</ul>

<div class="mw-heading mw-heading2"><h2 id="Support_chips">Support chips</h2></div>

<ul><li><a href="Intel_8237" title="Intel 8237">Intel 8237</a>: direct memory access (DMA) controller</li>

<li><a href="Intel_8251" title="Intel 8251">Intel 8251</a>: universal synchronous/asynchronous receiver/transmitter at 19.2 kbit/s</li>

<li><a href="Intel_8253" title="Intel 8253">Intel 8253</a>: programmable interval timer, 3x 16-bit max 10 MHz</li>

<li><a href="Intel_8255" title="Intel 8255">Intel 8255</a>: programmable peripheral interface, 3x 8-bit I/O pins used for printer connection etc.</li>

<li><a href="Intel_8259" title="Intel 8259">Intel 8259</a>: programmable interrupt controller</li>

<li><a href="Intel_8279" title="Intel 8279">Intel 8279</a>: keyboard/display controller, scans a keyboard matrix and display matrix like <a href="Seven-segment_display" title="Seven-segment display">7-seg</a></li>

<li><a href="Intel_8282" title="Intel 8282">Intel 8282</a>/<a href="Intel_8283" title="Intel 8283">8283</a>: 8-bit latch</li>

<li><a href="Intel_8284" title="Intel 8284">Intel 8284</a>: clock generator</li>

<li>Intel 8286/8287: bidirectional 8-bit driver. In 1980 both Intel I8286/I8287 (industrial grade) version were available for US$16.25 in quantities of 100.<a href="#cite_note-Intel_Preview_Special_Issue_1980,_page_29-32">[19]</a></li>

<li><a href="Intel_8288" title="Intel 8288">Intel 8288</a>: bus controller</li>

<li><a href="Intel_8289" title="Intel 8289">Intel 8289</a>: bus arbiter</li>

<li><a href="Floppy-disk_controller" title="Floppy-disk controller">NEC μPD765 or Intel 8272A</a>: floppy controller<a href="#cite_note-44">[29]</a></li></ul>

<div class="mw-heading mw-heading2"><h2 id="Microcomputers_using_the_8086">Microcomputers using the 8086</h2></div>

<ul><li>The Intel <a href="Multibus" title="Multibus">Multibus</a>-compatible <a href="Single-board_computer" title="Single-board computer">single-board computer</a> ISBC 86/12 was announced in 1978.<a href="#cite_note-45">[30]</a></li>

<li>The <a href="Xerox_NoteTaker" title="Xerox NoteTaker">Xerox NoteTaker</a> was one of the earliest <a href="Portable_computer" title="Portable computer">portable computer</a> designs in 1978 and used three 8086 chips (as CPU, graphics processor, and I/O processor), but never entered commercial production.</li>

<li><a href="Seattle_Computer_Products" title="Seattle Computer Products">Seattle Computer Products</a> shipped <a href="S-100_bus" title="S-100 bus">S-100 bus</a> based 8086 systems (SCP200B) as early as November 1979.</li>

<li>The Norwegian <a href="Mycron" title="Mycron">Mycron</a> 2000, introduced in 1980.</li>

<li>One of the most influential microcomputers of all, the <a href="IBM_PC" class="mw-redirect" title="IBM PC">IBM PC</a>, used the <a href="Intel_8088" title="Intel 8088">Intel 8088</a>, a version of the 8086 with an 8-bit <a href="Bus_(computing)" title="Bus (computing)">data bus</a> (as mentioned above).</li>

<li>The first <a href="Compaq_Deskpro" title="Compaq Deskpro">Compaq Deskpro</a> used an 8086 running at 7.16 MHz, but was compatible with add-in cards designed for the 4.77 MHz <a href="IBM_PC_XT" class="mw-redirect" title="IBM PC XT">IBM PC XT</a> and could switch the CPU down to the lower speed (which also switched in a memory bus buffer to simulate the 8088's slower access) to avoid software timing issues.</li>

<li>An 8 MHz 8086-2 was used in the <a href="Olivetti_M24" title="Olivetti M24">AT&T 6300 PC</a> (built by <a href="Olivetti" title="Olivetti">Olivetti</a>, and known globally under several brands and model numbers), an IBM PC-compatible desktop microcomputer. The M24 / PC 6300 has IBM PC/XT compatible 8-bit expansion slots, but some of them have a proprietary extension providing the full 16-bit data bus of the 8086 CPU (similar in concept to the 16-bit slots of the <a href="IBM_PC_AT" class="mw-redirect" title="IBM PC AT">IBM PC AT</a>, but different in the design details, and physically incompatible), and all system peripherals including the onboard video system also enjoy 16-bit data transfers. The later Olivetti M24SP featured an 8086-2 running at the full maximum 10 MHz.</li>

<li>The <a href="IBM_Personal_System/2" class="mw-redirect" title="IBM Personal System/2">IBM PS/2</a> models <a href="IBM_PS/2_Model_25" title="IBM PS/2 Model 25">25</a> and <a href="IBM_PS/2_Model_30" title="IBM PS/2 Model 30">30</a> were built with an 8 MHz 8086.</li>

<li>The <a href="Amstrad_PC1512" title="Amstrad PC1512">Amstrad PC1512</a>, <a href="Amstrad_PC1640" class="mw-redirect" title="Amstrad PC1640">PC1640</a>, PC2086, PC3086 and PC5086 all used 8086 CPUs at 8 MHz.</li>

<li>The <a href="Tandy_1000" title="Tandy 1000">Tandy 1000</a> SL-series and RL machines used 9.47 MHz 8086 CPUs.</li>

<li>The <a href="IBM_Displaywriter" class="mw-redirect" title="IBM Displaywriter">IBM Displaywriter</a> word processing machine<a href="#cite_note-InfoWorld_Aug_1982-46">[31]</a> and the Wang Professional Computer, manufactured by <a href="Wang_Laboratories" title="Wang Laboratories">Wang Laboratories</a>, also used the 8086.</li>

<li><a href="NASA" title="NASA">NASA</a> used original 8086 CPUs on equipment for ground-based maintenance of the <a href="Space_Shuttle_Discovery" title="Space Shuttle Discovery">Space Shuttle Discovery</a> until the end of the space shuttle program in 2011. This decision was made to prevent <a href="Software_regression" title="Software regression">software regression</a> that might result from upgrading or from switching to imperfect clones.<a href="#cite_note-47">[32]</a></li>

<li>KAMAN Process and Area Radiation Monitors<a href="#cite_note-48">[33]</a></li>

<li>The <a href="Tektronix" title="Tektronix">Tektronix</a> 4170 ran <a href="CP/M-86" title="CP/M-86">CP/M-86</a> and used an 8086 <style data-mw-deduplicate="TemplateStyles:r1238218222">

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</style><cite class="citation cs2"><a rel="nofollow" class="external text" href="https://bitsavers.org/pdf/tektronix/4170/061-2880-00_4170_Local_Graphics_Processing_Unit_Instruction_Manual_Apr1984.pdf">4170 Local Graphics Processing Unit Instruction Manual</a> (PDF)</cite></li></ul>

<ul><li><a href="Transistor_count" title="Transistor count">Transistor count</a></li>

<div class="mw-heading mw-heading2"><h2 id="Notes">Notes</h2></div>

<li id="cite_note-8"><a href="#cite_ref-8">^</a> Fewer TTL buffers, latches, multiplexers (although the amount of TTL logic was not drastically reduced). It also permits the use of cheap 8080-family ICs, where the 8254 CTC, <a href="Intel_8255" title="Intel 8255">8255</a> PIO, and 8259 PIC were used in the IBM PC design. In addition, it makes PCB layout simpler and boards cheaper, as well as demanding fewer (1- or 4-bit wide) DRAM chips.

</li>

<li id="cite_note-9"><a href="#cite_ref-9">^</a> using enhancement load <a href="PMOS_logic" title="PMOS logic">PMOS logic</a> (requiring 14 <a href="Volt" title="Volt">V</a>, achieving TTL compatibility by having VCC at +5 V and VDD at −9 V).

</li>

<li id="cite_note-11"><a href="#cite_ref-11">^</a> Made possible with depletion-load nMOS logic (the 8085 was later made using HMOS processing, just like the 8086).

</li>

<li id="cite_note-14"><a href="#cite_ref-14">^</a> Rev.0 of the instruction set and architecture was ready in about three months, according to Morse.

</li>

<li id="cite_note-15"><a href="#cite_ref-15">^</a> Using <a href="Rubylith" title="Rubylith">rubylith</a>, light boards, rulers, electric erasers, and a <a href="Digitizer" class="mw-redirect" title="Digitizer">digitizer</a> (according to Jenny Hernandez, member of the 8086 design team, in a statement made on Intel's webpage for its 25th birthday).

</li>

<li id="cite_note-16"><a href="#cite_ref-16">^</a> 8086 used less microcode than many competitors' designs, such as the MC68000 and others

</li>

<li id="cite_note-18"><a href="#cite_ref-18">^</a> Fast static RAMs in MOS technology (as fast as bipolar RAMs) was an important product for Intel during this period.

</li>

<li id="cite_note-19"><a href="#cite_ref-19">^</a> CHMOS is Intel's name for CMOS circuits manufactured using processing steps very similar to <a href="HMOS" class="mw-redirect" title="HMOS">HMOS</a>.

</li>

<li id="cite_note-20"><a href="#cite_ref-20">^</a> Other members of the design team were Peter A.Stoll and Jenny Hernandez.

</li>

<li id="cite_note-22"><a href="#cite_ref-22">^</a> The IBM PC and PC/XT use an Intel 8088 running in maximum mode, which allows the CPU to work with an optional 8087 coprocessor installed in the math coprocessor socket on the PC or PC/XT mainboard. (The PC and PC/XT may require maximum mode for other reasons, such as perhaps to support the DMA controller.)

</li>

<li id="cite_note-26"><a href="#cite_ref-26">^</a> Some 80186 clones did change the shift value, but were never commonly used in desktop computers.

</li>

<li id="cite_note-29"><a href="#cite_ref-29">^</a> (IBM PC used 4.77 MHz, 4/3 the standard NTSC <a href="Color_burst" class="mw-redirect" title="Color burst">color burst</a> frequency)

</li>

</ol></div>

<div class="mw-heading mw-heading2"><h2 id="References">References</h2></div>

<li id="cite_note-1"><a href="#cite_ref-1">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpushack.com/life-cycle-of-cpu.html">"The Life Cycle of a CPU"</a>. www.cpushack.com. Retrieved 26 January 2025.</cite>

</li>

<li id="cite_note-2"><a href="#cite_ref-2">^</a> Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2

</li>

<li id="cite_note-3"><a href="#cite_ref-3">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20070706032836/http://www.intel.com/museum/online/hist_micro/hof/">"Microprocessor Hall of Fame"</a>. Intel. Archived from <a rel="nofollow" class="external text" href="http://www.intel.com/museum/online/hist%5Fmicro/hof/">the original</a> on 2007-07-06. Retrieved 2007-08-11.</cite>

</li>

<li id="cite_note-i286-4"><a href="#cite_ref-i286_4-0">^</a> <cite class="citation book cs1"><a rel="nofollow" class="external text" href="http://bitsavers.org/components/intel/80286/210498-001_iAPX_286_Programmers_Reference_1983.pdf">iAPX 286 Programmer's Reference</a> (PDF). Intel. 1983. p. 1-1.</cite>

</li>

<li id="cite_note-Intel-5">^ <a href="#cite_ref-Intel_5-0">a</a> <a href="#cite_ref-Intel_5-1">b</a> <cite class="citation pressrelease cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20230212150554/https://newsroom.intel.com/news/intel-i7-8086k-processor/">"Happy Birthday, 8086: Limited-Edition 8th Gen Intel Core i7-8086K Delivers Top Gaming Experience"</a>. Intel Newsroom (Press release). Intel. 5 June 2018. Archived from <a rel="nofollow" class="external text" href="https://newsroom.intel.com/news/intel-i7-8086k-processor/">the original</a> on 12 February 2023.</cite>

</li>

<li id="cite_note-6"><a href="#cite_ref-6">^</a> <cite id="CITEREFŠojatSkalaRoginaŠkoda2016" class="citation book cs1">Šojat, Z.; Skala, K.; Rogina, B.M.; Škoda, P.; Sović, I. (2016). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=yM1sCwAAQBAJ&pg=PA67">"Implementation of Advanced Historical Computer Architectures §2.5 Microprocessors"</a>. In Szewczyk, R.; Kaštelan, I.; Temerinac, M.; Barak, M.; Sruk, V. (eds.). Embedded Engineering Education. Springer. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-3-319-27540-6</bdi>.</cite>

</li>

<li id="cite_note-7"><a href="#cite_ref-7">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://timeline.intel.com/1979/the-8088-processor">"The 8088 Processor"</a>. timeline.intel.com. Intel. Retrieved 26 January 2025.</cite>

</li>

<li id="cite_note-10"><a href="#cite_ref-10">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/8080/">"8080 family"</a>. CPU World.</cite>

</li>

<li id="cite_note-12"><a href="#cite_ref-12">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.pcworld.com/article/535966/article-7512.html">"Birth of a standard: The Intel 8086 microprocessor turns 40 today"</a>. PCWorld. Retrieved 2025-03-08.</cite>

</li>

<li id="cite_note-Scanlon_1988-13"><a href="#cite_ref-Scanlon_1988_13-0">^</a> <cite id="CITEREFScanlon1988" class="citation book cs1">Scanlon, Leo J. (1988). <a rel="nofollow" class="external text" href="https://archive.org/details/8086808880286ass0000scan/page/12">8086/8088/80286 assembly language</a>. Brady Books. p. <a rel="nofollow" class="external text" href="https://archive.org/details/8086808880286ass0000scan/page/12">12</a>. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0-13-246919-7</bdi>. <q>[…] The <a href="8086" class="mw-redirect" title="8086">8086</a> is software-compatible with the <a href="8080" class="mw-redirect" title="8080">8080</a> at the assembly-language level. […]</q></cite>

</li>

<li id="cite_note-17"><a href="#cite_ref-17">^</a> <cite id="CITEREFGeigerAllenStrader1990" class="citation book cs1">Geiger, Randall L.; Allen, Phillip E.; Strader, Noel R. (1990). "Random Logic vs. Structured Logic Forms". VLSI design techniques for analog and digital circuits. McGraw-Hill. p. 779. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>0-07-023253-9</bdi>.</cite> — Illustration of use of "random" describing CPU control logic

</li>

<li id="cite_note-21"><a href="#cite_ref-21">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://devicehunt.com/view/type/pci/vendor/8086">"PCI\VEN_8086 - Intel Corporation"</a>. Device Hunt. 2025-08-04. Retrieved 2025-08-14.</cite>

</li>

<li id="cite_note-23"><a href="#cite_ref-23">^</a> <cite id="CITEREFIntel_Corporation1983" class="citation book cs1">Intel Corporation (1983). IAPX 86, 88, 186, and 188 user's manual : programmer's reference. Intel. pp. 3–5. <a href="ISBN_(identifier)" class="mw-redirect" title="ISBN (identifier)">ISBN</a> <bdi>978-0835930352</bdi>. <a href="OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/11091251">11091251</a>.</cite>

</li>

<li id="cite_note-24"><a href="#cite_ref-24">^</a> <cite id="CITEREFSedory" class="citation web cs1">Sedory, Daniel B. <a rel="nofollow" class="external text" href="https://thestarman.pcministry.com/asm/debug/Segments.html">"The Segment:Offset Addressing Scheme"</a>. thestarman.pcministry.com. Retrieved 6 March 2025.</cite>

</li>

<li id="cite_note-25"><a href="#cite_ref-25">^</a> <cite id="CITEREFMorseRavenelMazorPohlman1980" class="citation journal cs1">Morse, Stephen P.; Ravenel, Bruce W; Mazor, Stanley; Pohlman, William B. (October 1980). <a rel="nofollow" class="external text" href="https://stevemorse.org/8086history/8086history.doc">"Intel Microprocessors: 8008 to 8086"</a>. IEEE Computer. 13 (10): 42–60. <a href="Doi_(identifier)" class="mw-redirect" title="Doi (identifier)">doi</a>:<a rel="nofollow" class="external text" href="https://doi.org/10.1109%2FMC.1980.1653375">10.1109/MC.1980.1653375</a>. <a href="S2CID_(identifier)" class="mw-redirect" title="S2CID (identifier)">S2CID</a> <a rel="nofollow" class="external text" href="https://api.semanticscholar.org/CorpusID:206445851">206445851</a>.</cite>

</li>

<li id="cite_note-8086Datasheet-27">^ <a href="#cite_ref-8086Datasheet_27-0">a</a> <a href="#cite_ref-8086Datasheet_27-1">b</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://web.archive.org/web/20211126175101/https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf">"8086 16-BIT HMOS Processor datasheet"</a> (PDF). Intel. Archived from <a rel="nofollow" class="external text" href="https://cdn.datasheetspdf.com/pdf-down/8/0/8/8086_Intel.pdf">the original</a> (PDF) on 26 November 2021. Retrieved 26 November 2021.</cite>

</li>

<li id="cite_note-28"><a href="#cite_ref-28">^</a> <cite class="citation book cs1"><a href="MASM" class="mw-redirect" title="MASM">Microsoft Macro Assembler 5.0 Reference Manual</a>. Microsoft Corporation. 1987. <q>Timings and encodings in this manual are used with permission of Intel and come from the following publications: Intel Corporation. iAPX 86, 88, 186 and 188 User's Manual, Programmer's Reference, Santa Clara, Calif. 1986.</q></cite> (Similarly for iAPX 286, 80386, 80387.)

</li>

<li id="cite_note-Intel79-31">^ <a href="#cite_ref-Intel79_31-0">a</a> <a href="#cite_ref-Intel79_31-1">b</a> <a href="#cite_ref-Intel79_31-2">c</a> <cite class="citation book cs1">The 8086 Family User's Manual. Intel Corporation. October 1979. p. B-1. <a href="OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/65699372">65699372</a>.</cite>

</li>

<li id="cite_note-Intel_Preview_Special_Issue_1980,_page_29-32">^ <a href="#cite_ref-Intel_Preview_Special_Issue_1980,_page_29_32-0">a</a> <a href="#cite_ref-Intel_Preview_Special_Issue_1980,_page_29_32-1">b</a> <a href="#cite_ref-Intel_Preview_Special_Issue_1980,_page_29_32-2">c</a> <a href="#cite_ref-Intel_Preview_Special_Issue_1980,_page_29_32-3">d</a> <a href="#cite_ref-Intel_Preview_Special_Issue_1980,_page_29_32-4">e</a> <cite id="CITEREFIntel_Corporation1980" class="citation journal cs1">Intel Corporation (May–June 1980). "8086 Available for industrial environment". Intel Preview (Special Issue: 16-Bit Solutions): 29. <a href="OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/803251993">803251993</a>.</cite>

</li>

<li id="cite_note-33"><a href="#cite_ref-33">^</a> <cite class="citation web cs1"><a rel="nofollow" class="external text" href="https://www.intel.com/pressroom/kits/quickrefyr.htm">"Intel® Microprocessor Quick Reference Guide - Year"</a>. www.intel.com.</cite>

</li>

<li id="cite_note-34"><a href="#cite_ref-34">^</a> <cite id="CITEREFIntel_Corporation1980" class="citation journal cs1">Intel Corporation (May–June 1980). "The 8086 Family: Concepts and realities". Intel Preview (Special Issue: 16-Bit Solutions): 19. <a href="ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/1041-8547">1041-8547</a>. <a href="OCLC_(identifier)" class="mw-redirect" title="OCLC (identifier)">OCLC</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/oclc/10331599">10331599</a>.</cite>

</li>

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<li id="cite_note-InfoWorld_Aug_1982-46"><a href="#cite_ref-InfoWorld_Aug_1982_46-0">^</a> <cite id="CITEREFZachmann1982" class="citation magazine cs1">Zachmann, Mark (August 23, 1982). <a rel="nofollow" class="external text" href="https://books.google.com/books?id=VDAEAAAAMBAJ&pg=PA57">"Flaws in IBM Personal Computer frustrate critic"</a>. <a href="InfoWorld" title="InfoWorld">InfoWorld</a>. Vol. 4, no. 33. pp. 57–58. <a href="ISSN_(identifier)" class="mw-redirect" title="ISSN (identifier)">ISSN</a> <a rel="nofollow" class="external text" href="https://search.worldcat.org/issn/0199-6649">0199-6649</a>. <q>the IBM Displaywriter is noticeably more expensive than other industrial micros that use the 8086.</q></cite>

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<div class="mw-heading mw-heading2"><h2 id="External_links">External links</h2></div>

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<div class="side-box-text plainlist">Wikimedia Commons has media related to <a href="https://commons.wikimedia.org/wiki/Category:Intel_8086" class="extiw external" title="commons:Category:Intel 8086">Intel 8086</a>.</div></div>

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<ul><li><a rel="nofollow" class="external text" href="http://datasheets.chipdb.org/Intel/x86/808x/datashts/8086">Intel datasheets</a></li>

<li><a rel="nofollow" class="external text" href="https://www.cpu-world.com/CPUs/8086/">List of 8086 CPUs and their clones at CPUworld.com</a></li>

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<li><a rel="nofollow" class="external text" href="http://matthieu.benoit.free.fr/cross/data_sheets/Intel_8086_users_manual.htm">The 8086 User's manual October 1979 INTEL Corporation</a> (<a href="PDF" title="PDF">PDF</a> document)</li>

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</style><div id="Intel_processors144" style="font-size:114%;margin:0 4em"><a href="List_of_Intel_processors" title="List of Intel processors">Intel processors</a></div></th></tr><tr><th scope="row" class="navbox-group" style="width:1%">Lists</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="List_of_Intel_processors" title="List of Intel processors">Processors</a>

<li><a href="List_of_Intel_Celeron_processors" title="List of Intel Celeron processors">Celeron</a></li>

<li><a href="List_of_Intel_Pentium_processors" title="List of Intel Pentium processors">Pentium</a>

<li><a href="Intel_Quark#List_of_Intel_Quark_processors" title="Intel Quark">Quark</a></li>

<li><a href="List_of_Intel_Itanium_processors" title="List of Intel Itanium processors">Itanium</a></li></ul></li>

<li><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></li>

<li><a href="List_of_Intel_chipsets" title="List of Intel chipsets">Chipsets</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="List_of_Intel_CPU_microarchitectures" title="List of Intel CPU microarchitectures">Microarchitectures</a></th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Pentium_M" title="Pentium M">P6 variant (Pentium M)</a></li>

<li><a href="Yonah_(microprocessor)" title="Yonah (microprocessor)">P6 variant (Enhanced Pentium M)</a></li></ul></li>

<li><a href="NetBurst" title="NetBurst">NetBurst</a></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Penryn_(microarchitecture)" title="Penryn (microarchitecture)">Penryn</a></li></ul></li>

<li><a href="Nehalem_(microarchitecture)" title="Nehalem (microarchitecture)">Nehalem</a>

<ul><li><a href="Westmere_(microarchitecture)" title="Westmere (microarchitecture)">Westmere</a></li></ul></li>

<li><a href="Sandy_Bridge" title="Sandy Bridge">Sandy Bridge</a>

<ul><li><a href="Ivy_Bridge_(microarchitecture)" title="Ivy Bridge (microarchitecture)">Ivy Bridge</a></li></ul></li>

<li><a href="Haswell_(microarchitecture)" title="Haswell (microarchitecture)">Haswell</a>

<ul><li><a href="Broadwell_(microarchitecture)" title="Broadwell (microarchitecture)">Broadwell</a></li></ul></li>

<li><a href="Skylake_(microarchitecture)" title="Skylake (microarchitecture)">Skylake</a>

<ul><li><a href="Cannon_Lake_(microprocessor)" title="Cannon Lake (microprocessor)">Cannon Lake</a></li></ul></li>

<li><a href="Sunny_Cove_(microarchitecture)" title="Sunny Cove (microarchitecture)">Sunny Cove</a>

<ul><li><a href="Cypress_Cove_(microarchitecture)" class="mw-redirect" title="Cypress Cove (microarchitecture)">Cypress Cove</a></li></ul></li>

<li><a href="Willow_Cove" title="Willow Cove">Willow Cove</a></li>

<li><a href="Golden_Cove" title="Golden Cove">Golden Cove</a>

<ul><li><a href="Raptor_Cove" class="mw-redirect" title="Raptor Cove">Raptor Cove</a></li></ul></li>

<li>Redwood Cove</li>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X86" title="X86">x86</a> <a href="Ultra-low-voltage_processor" title="Ultra-low-voltage processor">ULV</a></th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Bonnell_(microarchitecture)" title="Bonnell (microarchitecture)">Bonnell</a>

<ul><li><a href="Saltwell_(microarchitecture)" class="mw-redirect" title="Saltwell (microarchitecture)">Saltwell</a></li>

<li><a href="Silvermont" title="Silvermont">Silvermont</a></li></ul></li>

<li><a href="Goldmont" title="Goldmont">Goldmont</a>

<ul><li><a href="Goldmont_Plus" title="Goldmont Plus">Goldmont Plus</a></li></ul></li>

<li><a href="Tremont_(microarchitecture)" title="Tremont (microarchitecture)">Tremont</a>

<ul><li><a href="Gracemont_(microarchitecture)" title="Gracemont (microarchitecture)">Gracemont</a></li></ul></li>

<li>Crestmont</li></ul>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Current products</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th id="x86-64_(64-bit)40" scope="row" class="navbox-group" style="width:8.5em"><a href="X86-64" title="X86-64">x86-64</a> (<a href="64-bit_computing" title="64-bit computing">64-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="padding:0"><div style="padding:0 0.25em">

<li><a href="Celeron" title="Celeron">Celeron</a></li>

<li><a href="Pentium" title="Pentium">Pentium</a></li>

<li><a href="Intel_Core#Core_and_Core_Ultra_3/5/7/9" title="Intel Core">Core Ultra</a>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Discontinued</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em"></div><table class="nowraplinks navbox-subgroup" style="border-spacing:0"><tbody><tr><th scope="row" class="navbox-group" style="width:1%"><a href="Binary-coded_decimal" title="Binary-coded decimal">BCD</a> oriented (<a href="4-bit_computing" title="4-bit computing">4-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">pre-x86 (<a href="8-bit_computing" title="8-bit computing">8-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Early <a href="X86" title="X86">x86</a> (<a href="16-bit_computing" title="16-bit computing">16-bit</a>)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="X87" title="X87">x87</a> (external <a href="Floating-point_unit" title="Floating-point unit">FPUs</a>)</th><td class="navbox-list-with-group navbox-list navbox-odd" style="width:100%;padding:0"><div style="padding:0 0.25em">

<dl><dt>8/16-bit databus</dt>

<dt>16-bit databus</dt>

<dt>32-bit databus</dt>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%"><a href="IA-32" title="IA-32">IA-32</a> (<a href="32-bit_computing" title="32-bit computing">32-bit</a> x86)</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<li><a href="RapidCAD" title="RapidCAD">RapidCAD</a></li>

<li><a href="I486_OverDrive" title="I486 OverDrive">OverDrive</a></li></ul></li>

<li><a href="Celeron" title="Celeron">Celeron</a> (1998)

<li><a href="Pentium" title="Pentium">Pentium</a>

<ul><li><a href="Pentium_(original)" title="Pentium (original)">Original i586</a></li>

<li><a href="Pentium_OverDrive" title="Pentium OverDrive">OverDrive</a></li>

<ul><li><a href="List_of_Intel_P6-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel P6-based Xeon microprocessors">P6-based</a></li>

<li><a href="List_of_Intel_NetBurst-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel NetBurst-based Xeon microprocessors">NetBurst-based</a></li>

<li><a href="List_of_Intel_Core-based_Xeon_microprocessors" class="mw-redirect" title="List of Intel Core-based Xeon microprocessors">Core-based</a></li></ul></li>

<li><a href="Intel_Quark" title="Intel Quark">Quark</a></li>

<li><a href="Tolapai" title="Tolapai">Tolapai</a></li></ul>

<li><a href="Celeron" title="Celeron">Celeron</a>

<li><a href="Pentium" title="Pentium">Pentium</a>

<li><a href="Pentium_D#Smithfield_XE" title="Pentium D">Extreme Edition</a></li>

<ul><li><a href="List_of_Intel_Xeon_processors_(Nehalem-based)" title="List of Intel Xeon processors (Nehalem-based)">Nehalem-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Sandy_Bridge-based)" title="List of Intel Xeon processors (Sandy Bridge-based)">Sandy Bridge-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Ivy_Bridge-based)" title="List of Intel Xeon processors (Ivy Bridge-based)">Ivy Bridge-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Haswell-based)" title="List of Intel Xeon processors (Haswell-based)">Haswell-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Broadwell-based)" title="List of Intel Xeon processors (Broadwell-based)">Broadwell-based</a></li>

<li><a href="List_of_Intel_Xeon_processors_(Skylake-based)" title="List of Intel Xeon processors (Skylake-based)">Skylake-based</a></li></ul></li></ul>

</div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Other</th><td class="navbox-list-with-group navbox-list navbox-even" style="width:100%;padding:0"><div style="padding:0 0.25em">

<dd><a href="Itanium" title="Itanium">Itanium</a></dd>

<dd><a href="StrongARM" title="StrongARM">StrongARM</a></dd>

<dd><a href="XScale" title="XScale">XScale</a></dd></dl>

</div></td></tr></tbody></table><div></div></td></tr><tr><th scope="row" class="navbox-group" style="width:1%">Related</th><td class="navbox-list-with-group navbox-list navbox-odd hlist" style="width:100%;padding:0"><div style="padding:0 0.25em">

<ul><li><a href="Tick%E2%80%93tock_model" title="Tick–tock model">Tick–tock model</a></li>

<li><a href="Process%E2%80%93architecture%E2%80%93optimization_model" title="Process–architecture–optimization model">Process–architecture–optimization model</a></li>

<li><a href="List_of_Intel_graphics_processing_units" title="List of Intel graphics processing units">Intel GPUs</a>

<li><a href="Intel_Graphics_Technology" title="Intel Graphics Technology">Intel HD, UHD, and Iris Graphics</a></li>

<li><a href="PCI_IDE_ISA_Xcelerator" class="mw-redirect" title="PCI IDE ISA Xcelerator">PIIXs</a></li>

<li><a href="Stratix" title="Stratix">Stratix</a></li>

<li><a href="List_of_Intel_codenames" title="List of Intel codenames">Codenames</a></li>

<li><a href="Larrabee_(microarchitecture)" title="Larrabee (microarchitecture)">Larrabee</a></li></ul>

</div></td></tr></tbody></table></div>

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